Prior Art FIG. 1 illustrates an integrated circuit 100 constructed with bond pads around a periphery thereof, in accordance with the prior art. As shown, the integrated circuit 100 includes a semiconductor platform 101. Incorporated on the semiconductor platform 101 are a centrally-situated core 102 and a peripheral input/output (I/O) bus 104, which together define an “active circuit” of the integrated circuit 100. The I/O bus 104 is positioned around a periphery of the centrally-situated core 102.
Further included is a plurality of bond pads 106 which are disposed about the outer periphery of the I/O bus 104. As can be seen, the positioning of the bond pads 106 about the outer periphery of the I/O bus 104 requires that the overall size of the semiconductor platform 101 be augmented.
To further illustrate this, Prior Art FIG. 2 includes a cross-sectional view of the integrated circuit 100 of FIG. 1 taken along line 2-2. Similar to FIG. 1, the semiconductor platform 101 is shown to include the centrally-situated core 102 and I/O bus 104, which together define the “active circuit” of the integrated circuit 100 for processing electrical signals. Further shown are the bond pads 106 which require that the overall size of the semiconductor platform 101 be augmented.
FIG. 2 further illustrates underlying metal layers 206 that are interconnected by way of vias 208 for facilitating electric communication therebetween. As shown, the underlying metal layers 206 take-on a stacked configuration for allowing various unillustrated interconnections with the active circuit of the integrated circuit 100. Such underlying metal layers 206 are further coupled to the bond pads 106. Also included is a passivation layer 210 for protection purposes.
Trends toward increased circuit density and complexity in modem integrated circuit design have resulted in a desire for significant increases in both: 1) the number of input/output and power/ground pins per integrated circuit and, 2) the number of bond pads in order to connect to the package. To conserve active device area, it is desirable to reduce the bond pad pitch. However, smaller bond pads are more easily damaged by the large mechanical stresses inherent in the bonding process.
Generally, design rules have not allowed bonding pads over active areas, where they would be susceptible to damage from the large mechanical stresses of bonding. There is thus a continuing need to devise structures and layouts that satisfy the high-density requirements of advanced integrated circuit design and that would resist the high mechanical stresses of bonding.